For decades, shrinking transistors drove chip innovation. As Moore's law hits atomic limits, the age of one-chip-does-all comes to an end — the future is in specialized silicon.

In this future, chips cannot take years to design — hardware must evolve as ideas do. A new era of chip design and optimization is demanded.

We make AI tools that shorten the silicon design loop by an order of magnitude. Our work accelerates:

• Architectural exploration
• RTL construction
• Floorplanning, pin placement
• Clock-tree-synthesis
• Place & Route

Architect is currently being used on our own silicon. Our first hardware is an inference platform for Physical AI, outperforming the NVIDIA Jetson.

Our next work targets 7nm flows, and LLM-assisted hardware design.

We are 2 students who have worked on highly competitive silicon at Apple, AMD, and Tesla, across architectural, RTL, firmware, verification, and physical design stages.

You can learn more about us here and here.